Bug #706: Double peaking in ADC time (SH + PS)
Look at the correlation of BBCal signal ADC time with BBCal trigger TDC time (readout by 1190)
We looked at the correlation of BBCal signal ADC time with BBCal trigger time which get readout by a 1190 module situated in the TH crate. Here also we can clearly see a shift of about 12ns in the BBCal trigger trigger time. We take a copy of the BBCal trigger slightly before it goes to the TS to put that into a 1190 module. Then the TI of that module gets signal from the TS before opening the look-back window. So, seeing the same shift in 1190 output almost certainly indicate that the delay is coming from the TS itself.
After this finding, we tried to access the time sent out by the TI for each crate through replay to compare that with the time we get form TS and confirm the above mentioned inference. But accessing the time from TI didn't seem straight forward using the existing replay machinery. We'll reach out to the DAQ group to get help in this matter.