SoLID DAQ » SoLID preRD

h1. August 15th 2024

* VMM update

** Hall B planning to use VMM for uRWell detector. Front end card designed . Try L0 ATLAS mode with our card first, mode working very well. Ed has an utility to generate easily configuration file. Sergey has it running in his office and will move to EEL where detector is. Integrated with CODA already. L0 40 MHz clock, 250 MHz clock -> 41.66 MHz use external or TI clock 

** Continuous mode has issue if there are hot channels - Can only have one hit per window with the 250 ns 10 bit mode

** working with Shifa, VMM testing - had it working on virtual machine - can read out data - chip being tested, not clear if it is working - not change of ADC with change of DAC value - might try to get another chip

**rad hard components : lpGBT and rad hard bPol supplies - received - VTR+ will come later

** learning how to implement those components

*ESB

** need to get power in ESB

** can check with Eric Christy from detector group 

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