Project

General

Profile

Actions

August 24th 2023

*Orders **

VMM updates
*Ed working on 10 bit mode
*trying triggered mode by strobing the clock signal : can read with pulser
*4 prototypes board working
*Sergey used board with CODA and TI PCIe
*continuous trigger mode : bug in VMM for 10 bit, should be 40 buffers but does not work, so dead time until readout
*L0 mode : more stable, used by ATLAS, Ed implementing this mode, 8b/10b encoded data, only works in DDR mode, use over sampling to find the data
*VMM readout
*lpGBT FELIX
*ARISTA 10 gig
*LV Bpol
*need to follow up with Huong
*lpGBT order for TDIS and SoLID
*Need new FELIX board for lpGBT
*2 FELIX board due for JLab
  • 15 K$ FELIX
    *VTP
    *CODA compliant back, need TI data

Updated by Alexandre Camsonne 9 months ago · 1 revisions