February 25th 2021¶

*Updates
VMM3
*VMM + Eval board connected : can see good event, but reading several events have
bad values, seems cannot lock PLL, clock unstable, looks clean using internal FPGA clock

• limit at about 50 MB/s will write to file, could use two streams and socket to saturate ethernet link
  FADC update
  *simulation with FADC and TI : working
• preparing bitstream
• 40 gigE stack ~ 70 k$ for one project - 10 gigE one time fee : 5.5 K$
  MPD
  *will starting porting to VTP readout while
• 600 to 900 MB/s per link
  **Hanjie working on clustering C code done, working on synthesis to turn into FPGA code