July 16th 2020
  • Jeff back to working on board, pin out of FPGA abd check VMM IO (SVLS), not very good match with FPGA. VMM SVLS like signal center around 0.6 V. SAMPA also has SVLS signals too and readout by same FPGA as eval board. Series 7 Xlinx FPGA not directly compatible but working work around. Ultrascale FPGA support SVLS can be an option. Virtex 7 360$ / Ultrascale 1000 $ - might use ultrascale for more VMM3, October delivery time 2020 for Ultrascale ( has internal terminations too - need to check if on high performance or high range io )
    Need to double check when VMM3 would be delivered
    *CERN parts : need to be able to buy ( UVA ? or RD 51 )
    **APV25 : were taking cosmics - setup could be powered

*Compton short update ( Beatrice )

*SoLID preRD August 7th 2020
1) Original pre-R&D plan/goals Steve 15+5
2) GEM readout (Ed) 15+5
3) FADC developement (Ben) 15+5
4) Test stand ( Hanjie ) 15+5
5) Remaining tasks/ future work (Alexandre) 15 + 5

March 8th to 10th :Science review possibly

Updated by Alexandre Camsonne about 4 years ago · 1 revisions