July 2nd 2020 » History » Version 7
Alexandre Camsonne, 07/02/2020 03:13 PM
| 1 | 1 | Alexandre Camsonne | h1. July 2nd 2020 |
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| 2 | 2 | Alexandre Camsonne | |
| 3 | *Updates |
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| 4 | 6 | Alexandre Camsonne | **VMM3 : Jeff still working - Neigbhoring channel readout : CERN mapping is different with UVA - UVA is mapped one to one so should work and easy to implement - Radiation tolerance of FPGA : rad hardness for SEL (latchup) up to few 100 krads ( space grade 300 krad ) new FPGA, can design for SEU - support chip rad hardness : DC converter / regulator - 300 krad 5 K$ - regular around 100 $ : data for different experiment , might be able to handle radiation needed - avoid FET based regulator and use bipolar - can supply low voltage directly ( but trickier ) - checking parts which could work |
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| 7 | 3 | Alexandre Camsonne | |
| 8 | !https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210642.jpg! |
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| 9 | 4 | Alexandre Camsonne | |
| 10 | 5 | Alexandre Camsonne | !https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210632.jpg! |
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| 12 | !https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210711.jpg! |
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| 14 | 7 | Alexandre Camsonne | !https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210726.jpg! |
| 15 | 5 | Alexandre Camsonne | |
| 16 | 7 | Alexandre Camsonne | !https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210625.jpg! |
| 17 | 5 | Alexandre Camsonne | |
| 18 | !https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210711.jpg! |