July 30th 2020 » History » Revision 2
Revision 1 (Alexandre Camsonne, 07/30/2020 03:00 PM) → Revision 2/3 (Alexandre Camsonne, 07/30/2020 03:39 PM)
h1. July 30th 2020 *Updates **VMM3 : Jeff continuing on routing, tricky for inner pins - differential data line not super high speed but need to be well designed for 320 Mbit - Discussed with Hai - Ultrascale Eval board will be used to use with VMM eval board Going back to evaluation board next week, will try latest software Bryan compiled https://redmine.jlab.org/attachments/download/1010/vmm_readout_software-analog_generator-COMPILED.tgz Waiting for BNL order ROC chip : trying to contact to evaluate cost of making an ASIC - still need special design for ASIC to get them radiation hard in addition to TMR **APV25 : Ben still investigating - tried adding new oscillator - did not help - still jitter - most likely because of noisy power line - data line gets corrupted when data is sent - analog pll from general power rail ( not good because noise ) - voltage shift - will try to add more capacitance to reduce the shift , if does not work, go to half speed 1.25 Gbps *SoLID review talks ** GEM readout talk