June 25th 2020¶

Updates
*VMM : ESD settled, question if we need neighboring strips : yes, though need to make sure the mapping of GEM is correct with VMM mapping ( will check with Nilanga / Kondo ).
Power section for FPGA
Feast : DC DC converter option but might only plan for later depending availability
Estimate design completion by September 1
Could get VMM3 in 4 months
Bandwidth output from VMM to FPGA : 160 MHz dual edge 320 MBit - if can send all data to FPGA no need to use neighboring

Cost estimate to see if we can do two runs :

Transceiver : 100 $ 11 gigE

Components :

Timing resolution : 160 MHz timing resolution from clock, 6 ns timing output

*Discussion Compton asymmetry