June 4th 2020¶

• Options 1 for VMM3 readout, 4 chip per FPGA, use Felix and ROC
• Option 2 : 2 VMM to FPGA board, no Felix required, FPGA board exist
• Option 2 most straightforward

*APV25 : New firwmware - still debugging - now close to stable - need rate testing and zero supression - eventually
*VTP adapter board : start next week
**FADC VTP readout : ongoing