March 10th 2022 » History » Version 5
Alexandre Camsonne, 03/10/2022 04:04 PM
| 1 | 1 | Alexandre Camsonne | h1. March 10th 2022 |
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| 2 | 2 | Alexandre Camsonne | * Updates |
| 3 | ** VMM prototype |
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| 4 | 3 | Alexandre Camsonne | *** PCB about 8.8 K$ for 6 boards |
| 5 | *** waiting for quote for board |
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| 6 | *** still need to order lpGBT |
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| 7 | 1 | Alexandre Camsonne | ** VMM testing |
| 8 | 4 | Alexandre Camsonne | *** Xinzhan showing how to generate pile-up |
| 9 | *** Ed will provide material left overs to make a Faraday cage |
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| 10 | 1 | Alexandre Camsonne | * Discussion with Weizhi |
| 11 | 4 | Alexandre Camsonne | ** can still get TDO and regular readout but transfer 10x slower compared to direct output |
| 12 | ** Ed mentionned clock could be set at 320 MHz if needed |
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| 13 | |||
| 14 | * report |
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| 15 | ** working on text |
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| 16 | ** will add Xinzhan plots |