March 25th 2021
  • VMM
    • simulating 1 GBit interface for eval board
    • looking at 128 channels
    • using 20% of ressources - can implement triple logic sor SEU
    • when test direct readout GEM
    • have transition CARD from SAMPA - need to put it together might have all the parts
    • clock signal still need to be fixed
  • APV
    • highest rate 2.5 kHz 15 APV with 6 samples - expect 60 kHz -
      *FADC : Dave Abbott working on readout list - simulation looks good
      *UMass test stand : still working on optimization
      *Test lab path : use both readout possible - use VERSO and Ed's code -
      reset only when 10 bit done so can have both *