May 21st 2020

---meeting with USTC, file of board design, Jeff Wilson will help with the board. Ben could
FPGA radiation hard, TMR and SEU triple voting design, Xilinx FPGA space grade around 50 K$,
---advised not to use ROC, might try FPGA with redundancy
---hardcopy FPGA Altera ?
need table for requirements for experiment
--- need buffering - for direct readout path - up to 8 us to match FADC
--- ROC chip ( up to 8 VMM3 ) : VMM3 > ROC (ASIC) -> GBT
will look into getting ROC chips
--- FEAST ? replacement DC / DC converter rad hard ( from CERN too )
--- still need to compile the analog pulser version
--FADC : Ed done on FADC side, discussion with Dave on CODA format, working on buffering on FADC and VTP
--APV25 : tried new firmware with 8 MPDs, 12 connected, issues with some MPDs : MPD omits some channels - update to firmware - need to power cycle crate to reload ( Jack helped ) - seems issue was fixed - more testing - software work around ?
--ASOC : got pulser and scope for testing

Updated by Alexandre Camsonne about 4 years ago · 2 revisions