May 28th 2020

Agenda :
--prototype board for VMM : computed achievable trigger assumming single rates, assuming 400 ns windows, gives above 100 KHz of trigger rate
( 130 KHz if 15 MHz , about 180 KHz if 10 MHz ) could go higher if single rates lower or window smaller.
Possibility to double e-link for increase bandwidth for the high rate strips.
Chris : showing FPGA board used for RICH MAROC, could be use as started point
Time stamp at 160 MHz, gives timestamping at 6 ns resolution

Need to think about where electronics could be placed, seems VMM better than APV25 because it can handle
higher capacitance. Will discuss with Kondo and we will do testing.

Kondo : meeting about VMM production for RD51 SRS, ( 2K$ a wafer )

-Compton FADC studies

-SIDIS trigger requirements - FADC / GEM readout max trigger rate
Maximum trigger for FADC should be able to reach 200 KHz.
2 version of firmware ( triggered for Hall A and B ) , and Hall D firmware - plan for merging two firmware

-Discussion UMass test stand

Updated by Alexandre Camsonne almost 4 years ago · 1 revisions