May 6th 2021

• Updates
  • VMM
    • VHDL code at 1 gbit speed, going through GBT with 10 serial lines
    • PCB : working on power distribution, added signal lines with mezzanine to save space on board, move flash memory to mezzanine and JTAG
    • can make progress on VMM design rapidly
    • do not need to have both ethernet or GBT at same time so can save
    • 1 FPGA received from NewArk
    • some FPGA ordered from unauthorized source : cancelled - only 30 days warranty
    • new order should arrive before 30 weeks lead time
    • can use 040 or 035 : development board using 040 abour 3K$, could order a few (AVNET has 12 )
    • 4 chips : new order with AVNET through for regular FPGA, might get those in time (30 to 35 weeks )
    • could check for other board with this chip
    • need to follow up on special parts with Nilanga ( might be able to use some spare parts from SAMPA but needs to replenish stock )
    • VMM in customs
    • Need to follow up with George
  • APV
    • VTP readout completed
    • MPD APV readout still need to fix issues
  • FADC
    • 2 FADC readout - need add CODA GUI for controls
    • no performance test yet
      **UMass
    • took asymmetry test data, writing software
      **VMM
    • test with chamber in UVA in EEL clean room
    • getting starting with UVA setup for X-ray
    • adapter for the VMM eval board for direct **
      *start to think about CD1 needs
      *streaming workshop : quickly put number together SIDIS seems doable - need to do some studies