November 5th 2020¶
- Met with Gianluigi De Geronimo, getting the U Arizona design which is closer to GEM, he was concerned of pick up of DC DC converter by VMM, it seems we expect 100 k to 20 k electrons so we should have
- discussion of Ed for FPGA to ASIC conversion : SMU people might be able to produce this ASIC.
- license Vivado running on Ed computer,can continue development
- Jeff still working on layout, will look at AZ design for filtering and shielding of DC supply, connector with low resistance and inductance
- Optical to VXS 32 boards ordered
- enable VME320 on SSP readout
- show can reach 5 KHz
**UMass test stand : FADC issue , maximum word loaded is wrong, now decoder works. VTP header files missing which need to be added.
- ASOC : spare received still need to see signal
Updated by Alexandre Camsonne over 2 years ago · 2 revisions