October 15th 2020

• Updates
  • VMM3
    • working with FPGA eval board with VMM3 eval board - can talk the Xilinx Eval board - don't see the direct signal from eval board for now - issue with virtual machine crashing , when plugging things
    • Jeff still working on layout
    • tried continuous firmware, seems to work, could use the setup to send trigger to channel 63
    • L0 max width 8 clock cycles
  • APV25
    • testing the rate limit in INFN tomorrow or next week
    • QSFP to VXS out for quoting
    • multiple 10gigE easier - 10 gigE
  • UMass : FADC working with CODA, use TI internal trigger and use VTP
  • MAROC : still noise issue - special windowing to cancel

*Science review talk slides : add plan and status -

*Update SoLID collaboration