October 1st 2020¶
- protype : schematics being reviewed
- cable to send generator test board to test board made by Armen, can use pulser to pulse input of VMM3, will get two channel pulse generator used for MAROC testing
- George received email and will send us the continuous firmware. Is there a firmware number that can be read back ?
- FPGA eval board connected to Ed's PC, ready to load bit files. Next step put the mezannine board and after try readout SVLS signal. Need work on decoding of data. Software readout ? Ben has a HDL backend with 32 bit event builder and use socket directly from a PC.
- test with source for direct output : can start paperwork for radioactive source
- send mail for VMM3
- VXS readout : Ben working on VXS readout, doing the simulation
- APV25 : Paolo Musico working on integrating the MPD common noise and zero supression
- FADC crate still in Hall C will move to test lab for FADC / VETROC tests
- TDIS meeting : plan to make more SAMPA boards, but need GBT and other parts, so might be a way to procure. Thia looking into it.