SoLID DAQ » SoLID preRD

h1. September 10th 2020

* Updates

** VMM3

*** VMM prototype : Jeff working on layout and routing for standard pitch part, fine pitch part requires agressive design, some PCB companies might have trouble. 

*** Evaluation board : all components are on hand, need license for FPGA programming software ( free version does not support chip : Ultrascale ? ), might be able to have a 30 days evaluation, can write firmware but cannot test. Ed looked at schematics on the manual, need to be careful with signal input : could damage the FPGA 

4 V should be ok. Can have a generator , might try to access a scope. Could try to get the FPGA code to look closer and also use diagnostic tool on JTAG. Need to make a few macros for Ed to look at data.

*** Possibility to look at signal from GEMs in DAQ lab, GEM ready to go might be able to test with cosmics. Scintillators trigger available. Could look at direct output with DIN adapter, GEM to 40 pin headers, can make adapter to go from 40 pins to DIN to fit in VMM3. Ideally want to bring a radioactive source to generate background - but needs set up paperwork with radcon 

** APV : 

*** progress on INFN setup : Bryan can talk to all the module, TI are not TI master capable, will send trigger to SSP. TI with fibers 1 and 5 might not be able to do TI master. Link speed down to 1.25 Gbps, most likely still able to reach 100 KHz with 4 or 5 APV. Plan to test with 1 to 16 APV.

SRS : still many APV chip on single gigabit line. 4 APV / gigabit link

Could consider making a new board.

Final rate is occupancy driven : might be ok for SIDIS with about 25 % occupancy at max

*** VTP readout : Mark made the schematics of adapter - could be build in a pretty short time : 2 to 4 weeks

** Test stand

*** Hanjie : Bryan helping setting up CODA, Java issues but should be solved soon, start setting up modules and copying files from Compton. CODA check java version which number , CODA designed for 2 GB/s for 16 crates in Hall D, use of large amount of memory for optimization for Hall D, could cause issue is everything run on same computer. Issue at prestart when memory is allocated, Java VM might shut down if it runs out of memory. Java garbage collection : can run once but might not work a second time ( need to wait for garbage collection to occur ) , fix might be done in a few weeks. Provide different event builder using smaller footprint in memory.

Dave, Carl and Vardan testing on test setup. Other issue with platform with newer java version version greater than 255, so need to use older version. Issue of memory with 16 GB ram or less. Could provide jar using less memory. Welcome to contact coda@jlab.org or Dave or Bryan if you encounter issues.

*** moving VXS crate to test lab for MAROC test and VETROC CDET developement should be done next week

** preRD report : 

*** need update introduction and conclusion with plan for testing. Mention preRD DOE review : add paragraph

add high rate radioactive 

*** add pictures of test stand 

** Final preRD DAQ report not avalaible yet