September 17th 2020¶

• Updates
  • VMM3
    • prototype : going with larger package for FPGA 95 % certain, has extra IO bank, power and ground assignement next big tasks, several voltages to divide, use model from USTC.
    • evaluation : direct readout, cables done for plugging to FPGA eval board, will test first with current firmware
    • testing procedure VMM3 : test on wafer, from presentation yield was 72 %
    • GBT chips order : 35 $ (1 per board, mininum 4 board , have 4 on hand) , fiber optic module plug-in
    • Ethernet can be used but not very rad hard
    • eval board : could see data from board
    • RD51 :

• APV25 :
  • INFN clean room: Bryan looking at how many triggers can be received, SSP processing time quite slow right now. Test with different buffer level, need simulation of MPD to test what is happening.
    Common noise code ready to be set. Right now running 200 Hz need to optimize trigger rules expect 5 KHz if VME is not bottle neck.

• Optical adapter should be ready in next few week, ask for quotes : 4 MPDs per board

• UMass test stand : not use _ in CODA names

• update VXS
• Milestone E : May 2020 - need update

• MAROC