December 17th 2020

• Ecal

• Updates
  • VMM
    • met with Ben, progress on readout
    • measure time difference between clock from VMM to data, starting looking with probes
      6 bit ADC should come at raising edge of the clock, but looking at it sometimes happens on falling edge
      need two good differential probes to check
    • Ed plugged the VMM eval board to GEM chamber, will check everything ok before powering the GEM
    • asked to Gianluigi and Venetios for testing
  • APV
    • MPD : firmware to test fast readout - will try in TEDF
  • FADC
    • slides from Hanjie
    • same setup without busy signal
    • test with raw mode - change of rate - test without writing to disk - 80 samples
    • data rate - gigabit ethernet limit - and maybe VME limit