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December 3rd 2020 » History » Version 11

Alexandre Camsonne, 12/03/2020 04:21 PM

1 1 Alexandre Camsonne
h1. December 3rd 2020
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* Maroc Cerenkov tests https://redmine.jlab.org/attachments/download/1113/LaserTestQuestions.pdf
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** test linearity with LED
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*Updates
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** VMM
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*** 128 channels prototype : doing scaling from eval to 128 channels on-going, need to determine ressources used before the tripling method, trigger with window ( limit on how many trigger : 4 trigger in a windows - window size under 1 us ( 400 ns ? ) - can take a couple of MHz ) - TS can be programmed to allow only 4 triggers in the windows - need more processing power for more - trigger are counted, can realign data
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***  got NSW ALTIM file of Micromegas design - schematics have a lot of useful notes - 8 chips on small card - Jeff will look at it 
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*** VMM3 order ok end of January
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*** plan for december : finish eval readout direct output, processing of 128 channel code
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*** evaluatiom development board : VHDL code complete, got the 1 gigE examaple, some work with Ben to get it going, C++ software code running on linux ( done at the lab )
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** FADC UMass
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***use playback feature, helicity input for trigger and TI busy in FADC channel to measure deadtime
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*** small issue with TI random trigger, get twice expected rate, put signal to check rate measurement ( 30 Hz ), can check random rate with event type. Can check with a regular pulser from TI. William will check the firmware
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*** will try different bufferlevel and blocklevel, up to 20 KHz with block level and buffer level 1
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*** rate Trigger 2 is twice Trigger 1 - Trig 2 affected by TI busy ? 
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** APV
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*** progress, will need test setup, will use BigBite setup for now
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** ASOC
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** FADC  https://redmine.jlab.org/attachments/download/1112/FADC_dt2.pdf
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*Test ASOC https://redmine.jlab.org/attachments/download/1114/SoLID_cosmics.pdf pdf