February 25th 2021 » History » Version 1
Alexandre Camsonne, 02/25/2021 04:12 PM
| 1 | 1 | Alexandre Camsonne | h1. February 25th 2021 |
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| 2 | |||
| 3 | *Updates |
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| 4 | **VMM3 |
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| 5 | ***VMM + Eval board connected : can see good event, but reading several events have |
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| 6 | bad values, seems cannot lock PLL, clock unstable, looks clean using internal FPGA clock |
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| 7 | *** limit at about 50 MB/s will write to file, could use two streams and socket to saturate ethernet link |
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| 8 | **FADC update |
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| 9 | ***simulation with FADC and TI : working |
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| 10 | *** preparing bitstream |
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| 11 | *** 40 gigE stack ~ 70 k$ for one project - 10 gigE one time fee : 5.5 K$ |
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| 12 | **MPD |
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| 13 | ***will starting porting to VTP readout while |
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| 14 | *** 600 to 900 MB/s per link |
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| 15 | **Hanjie working on clustering C code done, working on synthesis to turn into FPGA code |