Project

General

Profile

February 25th 2021 » History » Version 2

Alexandre Camsonne, 02/25/2021 04:12 PM

1 1 Alexandre Camsonne
h1. February 25th 2021
2
3 2 Alexandre Camsonne
* Updates
4
** VMM3
5
*** VMM + Eval board connected : can see good event, but reading several events have
6 1 Alexandre Camsonne
bad values, seems cannot lock PLL, clock unstable, looks clean using internal FPGA clock
7
*** limit at about 50 MB/s will write to file, could use two streams and socket to saturate ethernet link
8 2 Alexandre Camsonne
** FADC update
9
*** simulation with FADC and TI : working
10 1 Alexandre Camsonne
*** preparing bitstream
11
*** 40 gigE stack ~ 70 k$ for one project - 10 gigE one time fee : 5.5 K$
12 2 Alexandre Camsonne
** MPD
13
*** will starting porting to VTP readout while
14 1 Alexandre Camsonne
*** 600 to 900 MB/s per link
15 2 Alexandre Camsonne
** Hanjie working on clustering C code done, working on synthesis to turn into FPGA code