July 2nd 2020 » History » Version 11
Alexandre Camsonne, 07/02/2020 03:21 PM
| 1 | 1 | Alexandre Camsonne | h1. July 2nd 2020 |
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| 2 | 2 | Alexandre Camsonne | |
| 3 | *Updates |
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| 4 | 6 | Alexandre Camsonne | **VMM3 : Jeff still working - Neigbhoring channel readout : CERN mapping is different with UVA - UVA is mapped one to one so should work and easy to implement - Radiation tolerance of FPGA : rad hardness for SEL (latchup) up to few 100 krads ( space grade 300 krad ) new FPGA, can design for SEU - support chip rad hardness : DC converter / regulator - 300 krad 5 K$ - regular around 100 $ : data for different experiment , might be able to handle radiation needed - avoid FET based regulator and use bipolar - can supply low voltage directly ( but trickier ) - checking parts which could work |
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| 6 | 11 | Alexandre Camsonne | Rad hard FPGA have built-in error correction and more immune to cell SEU |
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| 8 | Use 4 bit serial ( 1 bit serial at 70 MHz ) to reload faster - If have GBT, reserve some line for JTAG (GBT full duplex - and has SPI and I2C already ) |
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| 11 | 3 | Alexandre Camsonne | |
| 12 | !https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210642.jpg! |
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| 13 | 9 | Alexandre Camsonne | |
| 14 | !https://redmine.jlab.org/attachments/download/1017/IMG_20191203_210632.jpg! |
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| 15 | 10 | Alexandre Camsonne | |
| 16 | !https://redmine.jlab.org/attachments/download/1018/IMG_20191203_210711.jpg! |