July 2nd 2020 » History » Version 12

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Alexandre Camsonne, 07/02/2020 03:22 PM


July 2nd 2020

Updates
*VMM3 : Jeff still working - Neigbhoring channel readout : CERN mapping is different with UVA - UVA is mapped one to one so should work and easy to implement - Radiation tolerance of FPGA : rad hardness for SEL (latchup) up to few 100 krads ( space grade 300 krad ) new FPGA, can design for SEU - support chip rad hardness : DC converter / regulator - 300 krad 5 K$ - regular around 100 $ : data for different experiment , might be able to handle radiation needed - avoid FET based regulator and use bipolar - can supply low voltage directly ( but trickier ) - checking parts which could work

Rad hard FPGA have built-in error correction and more immune to cell SEU

Use 4 bit serial ( 1 bit serial at 70 MHz ) to reload faster - If have GBT, reserve some line for JTAG (GBT full duplex - and has SPI and I2C already )

IMG_20191203_210642.jpg (1.31 MB) Alexandre Camsonne, 07/02/2020 03:00 PM

IMG_20191203_210632.jpg (1.74 MB) Alexandre Camsonne, 07/02/2020 03:00 PM

IMG_20191203_210711.jpg (1.23 MB) Alexandre Camsonne, 07/02/2020 03:00 PM

IMG_20191203_210726.jpg (1.05 MB) Alexandre Camsonne, 07/02/2020 03:00 PM

IMG_20191203_210657.jpg (988 KB) Alexandre Camsonne, 07/02/2020 03:00 PM

IMG_20191203_210736.jpg (1.14 MB) Alexandre Camsonne, 07/02/2020 03:00 PM