July 30th 2020

Updates
*VMM3 : Jeff continuing on routing, tricky for inner pins - differential data line not super high speed but need to be well designed for 320 Mbit -
Discussed with Hai - Ultrascale Eval board will be used to use with VMM eval board
Going back to evaluation board next week, will try latest software Bryan compiled

https://redmine.jlab.org/attachments/download/1010/vmm_readout_software-analog_generator-COMPILED.tgz

Waiting for BNL order
ROC chip : trying to contact to evaluate cost of making an ASIC - still need special design for ASIC to get them radiation hard in addition to TMR

**APV25 : Ben still investigating - tried adding new oscillator - did not help - still jitter - most likely because of noisy power line
data line gets corrupted when data is sent
analog pll from general power rail ( not good because noise ) - voltage shift
- will try to add more capacitance to reduce the shift , if does not work, go to half speed 1.25 Gbps

*SoLID review talks
  • GEM readout talk

SoLID_preRD_Review_FADCReadout (2).pdf (1.63 MB) Alexandre Camsonne, 07/31/2020 11:55 AM

SoLID_preRD_Review_talk_v10.pptx (9.82 MB) Alexandre Camsonne, 08/03/2020 06:31 AM