June 18th 2020

  • Updates
    • VMM3 : Ed and Jeff working on the layout, good progress for front end and FPGA backend
      Output of VMM3 SLVS, not supported natively by FPGA but work around.
      People are back at the lab, work ongoing.
      10 gigE possible, might use 1 gigE copper first for lower rate applications
      Bryan fixed VMM software, will test next Moday
      Nilanga mentionning UV SBS chamber, could consider using VMM3 for read out during SBS ( next year )
      Distance and radiation profile to check
      Existing boards that could be used to look at direct output of eval boards

*APV25 : Danning : still testing - lower fiber speed firmware to check if stability improves - Ben wants to monitor the jitter of optical link - might be MPD jitter of optical signal which could generate errors - might need switch clock to improve if that is the case. Option to use external clock input/output . Need to have clock in a TDC for jitter correction ?
If TI used to distribute clock, can use time stamp. prescaled RF in TDC needed too.

Plan to send TI/TS clock to MPD - though clock will be 41.666 MHz instead of 40 MHz - Better test early to see if that works -
this was used during HPS - could use NIM modules or daisy chain for clock distribution - can compare the measurememt from phase with respect to clock -

*Cerenkov SoLID test 2nd run

CerTestSoLID.pdf (168 KB) Alexandre Camsonne, 06/18/2020 02:59 PM

CerTestSoLID.pptx (515 KB) Alexandre Camsonne, 06/18/2020 03:00 PM