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June 18th 2020 » History » Version 2

Alexandre Camsonne, 06/19/2020 10:54 AM

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h1. June 18th 2020
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* Updates
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** VMM3 : Ed and Jeff working on the layout, good progress for front end and FPGA backend
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   Output of VMM3 SLVS, not supported natively by FPGA but work around.
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   People are back at the lab, work ongoing. 
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   10 gigE possible, might use 1 gigE copper first for lower rate applications
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   Bryan fixed VMM software, will test next Moday
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   Nilanga mentionning UV SBS chamber, could consider using VMM3 for read out during SBS ( next year )
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   Distance and radiation profile to check
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   Test 
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   Existing boards that could be used to look at direct output of eval boards
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*APV25 : Danning : still testing - lower fiber speed firmware to check if stability improves - Ben wants to monitor the jitter of optical link - might be MPD jitter of optical signal which could generate  errors - might need switch clock to improve if that is the case. Option to use external clock input/output . Need to have clock in a TDC for jitter correction ? 
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If TI used to distribute clock, can use time stamp. prescaled RF in TDC needed too.
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Plan to send TI/TS clock to MPD - though clock will be 41.666 MHz instead of 40 MHz - Better test early to see if that works - 
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this was used during HPS - could use NIM modules or daisy chain for clock distribution - can compare the measurememt from phase with respect to clock -
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*Cerenkov SoLID test 2nd run