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June 25th 2020 » History » Version 2

Alexandre Camsonne, 06/25/2020 03:40 PM

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h1. June 25th 2020
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*Updates
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**VMM : ESD settled, question if we need neighboring strips : yes, though need to make sure the mapping of GEM is correct with VMM mapping ( will check with Nilanga / Kondo ). 
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Power section for FPGA 
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Feast : DC DC converter option but might only plan for later depending availability
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Estimate design completion by September 1
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Could get VMM3 in 4 months
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Bandwidth output from VMM to FPGA : 160 MHz dual edge  320 MBit - if can send all data to FPGA no need to use neighboring 
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Cost estimate to see if we can do two runs :
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Transceiver : 100 $ 11 gigE 
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Components : 
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Timing resolution : 160 MHz timing resolution from clock, 6 ns timing output 
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*Discussion Compton asymmetry