June 3rd 2021 » History » Version 3
Alexandre Camsonne, 06/03/2021 03:17 PM
| 1 | 1 | Alexandre Camsonne | h1. June 3rd 2021 |
|---|---|---|---|
| 2 | |||
| 3 | *Updates |
||
| 4 | 2 | Alexandre Camsonne | ** VMM |
| 5 | *** have chips |
||
| 6 | 3 | Alexandre Camsonne | *** started testing but don't see pulser signal - might be bad contact or bad chips - investigating low level tests - socket could have been damaged |
| 7 | *** test test program with our test boards : it worked |
||
| 8 | *** made cable to plug to power supply to check current : striped cable is center pin |
||
| 9 | *** Jeff working on front end layout for filtering - close to MM Arizona design - once done will run design with Gianluigi |
||
| 10 | *** simulating GBT link, code close to final version, testing with multiple inputs, gigabit ethernet can be tested too |
||
| 11 | *** estimate early July for first prototype |
||
| 12 | *** will run design through Ben and William too in next few days |
||
| 13 | 2 | Alexandre Camsonne | ** SoLID ECal |
| 14 | *** developement Ecal firmware, scalers and energy clusters - available end of the month for Hanjie |
||
| 15 | ** UMass |