June 3rd 2021 » History » Version 5
Alexandre Camsonne, 06/03/2021 03:33 PM
| 1 | 1 | Alexandre Camsonne | h1. June 3rd 2021 |
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| 3 | *Updates |
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| 4 | 2 | Alexandre Camsonne | ** VMM |
| 5 | *** have chips |
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| 6 | 3 | Alexandre Camsonne | *** started testing but don't see pulser signal - might be bad contact or bad chips - investigating low level tests - socket could have been damaged |
| 7 | *** test test program with our test boards : it worked |
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| 8 | *** made cable to plug to power supply to check current : striped cable is center pin |
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| 9 | *** Jeff working on front end layout for filtering - close to MM Arizona design - once done will run design with Gianluigi |
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| 10 | *** simulating GBT link, code close to final version, testing with multiple inputs, gigabit ethernet can be tested too |
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| 11 | *** estimate early July for first prototype |
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| 12 | *** will run design through Ben and William too in next few days |
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| 13 | 2 | Alexandre Camsonne | ** SoLID ECal |
| 14 | 4 | Alexandre Camsonne | *** developement Ecal firmware, scalers and energy clusters - available end of the month for Hanjie |
| 15 | *** FADC VTP readout already implemented, Dave testing right now |
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| 16 | ** APV25 |
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| 17 | *** Bryan working on MPD readout with VTP |
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| 18 | 2 | Alexandre Camsonne | ** UMass |
| 19 | 5 | Alexandre Camsonne | |
| 20 | * Possible plan for CD1 |
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| 21 | ** synergy with EIC |
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| 22 | ** plan for FY 22 |