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March 10th 2022
  • Updates
    • VMM prototype
      • PCB about 8.8 K$ for 6 boards
      • waiting for quote for board
      • still need to order lpGBT
    • VMM testing
      • Xinzhan showing how to generate pile-up
      • Ed will provide material left overs to make a Faraday cage
  • Discussion with Weizhi
    • can still get TDO and regular readout but transfer 10x slower compared to direct output
    • Ed mentionned clock could be set at 320 MHz if needed

  • report
    • working on text
    • will add Xinzhan plots

Updated by Alexandre Camsonne 7 months ago · 5 revisions