March 25th 2021 » History » Version 1
Alexandre Camsonne, 03/25/2021 03:28 PM
| 1 | 1 | Alexandre Camsonne | h1. March 25th 2021 |
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| 2 | * VMM |
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| 3 | ** simulating 1 GBit interface for eval board |
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| 4 | ** looking at 128 channels |
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| 5 | ** using 20% of ressources - can implement triple logic sor SEU |
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| 6 | ** when test direct readout GEM |
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| 7 | ** have transition CARD from SAMPA - need to put it together might have all the parts |
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| 8 | ** clock signal still need to be fixed |
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| 9 | * APV |
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| 10 | ** highest rate 2.5 kHz 15 APV with 6 samples - expect 60 kHz - |
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| 11 | *FADC : Dave Abbott working on readout list - simulation looks good |
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| 12 | *UMass test stand : still working on optimization |
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| 13 | *Test lab path : use both readout possible - use VERSO and Ed's code - |
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| 14 | reset only when 10 bit done so can have both |
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| 15 | * |