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March 4th 2021 » History » Version 1

Alexandre Camsonne, 03/04/2021 03:53 PM

1 1 Alexandre Camsonne
h1. March 4th 2021
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*Updates
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** VMM
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*** working on 128 channels firmware - complete and close to final - 8 x 16 channels group - operating same as the 12 channel module - 4 independent event building units - up to 4 triggers - ~ 5 MHz trigger rate for 800 ns
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windows - could extend to 6 or 8 if needed -  simulating 128 channel code ( ethernet not implemented yet )
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will get 1 gigE block to be added )  Ultrascale 035 chip use about 22% can fit TMR - still need to complete all simulation - could use 040 to get more resources - logic clocked at 160 MHz - 10 gigE on eval board ? could add SFP - 10gigE on PC available copper - could loop back for testing 10 gigE
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*** Eval board : still need to check connector / cable - software from Ben + additionnal processing - running on VM linux -  need use adapter ( already available )
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*** chips still being packaged - checking for the testing with China and borrowing CERN test system
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*** Jeff still working on layout - should plan to meet 
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with Gianluigi to review ( about 4 weeks )
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** FADC : waiting on Dave to start FADC VTP readout - MPD SSP code update - FADC firmware done
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** can set additionnal crate for VTP MPD - waiting for f 
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** MAROC : Bishnu looking at cosmics
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** GEM : bubbler - checking -
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** VMM : MIP around set around 20 ADC channels, pedestal noise about 2 ADC channel - If 100 mV signal gives ADC 6 pretty close from noise - will have to optimize gain - ( option to include higher gain in new batch of chip ) 
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*SoLID review next week
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** need prepare back up slides for DAQ question