SoLID DAQ » SoLID preRD

h1. March 4th 2021

*Updates

** VMM

*** working on 128 channels firmware - complete and close to final - 8 x 16 channels group - operating same as the 12 channel module - 4 independent event building units - up to 4 triggers - ~ 5 MHz trigger rate for 800 ns

windows - could extend to 6 or 8 if needed -  simulating 128 channel code ( ethernet not implemented yet )

will get 1 gigE block to be added )  Ultrascale 035 chip use about 22% can fit TMR - still need to complete all simulation - could use 040 to get more resources - logic clocked at 160 MHz - 10 gigE on eval board ? could add SFP - 10gigE on PC available copper - could loop back for testing 10 gigE

*** Eval board : still need to check connector / cable - software from Ben + additionnal processing - running on VM linux -  need use adapter ( already available )

*** chips still being packaged - checking for the testing with China and borrowing CERN test system

*** Jeff still working on layout - should plan to meet 

with Gianluigi to review ( about 4 weeks )

** FADC : waiting on Dave to start FADC VTP readout - MPD SSP code update - FADC firmware done

** can set additionnal crate for VTP MPD - waiting for f 

** MAROC : Bishnu looking at cosmics

** GEM : bubbler - checking -

** VMM : MIP around set around 20 ADC channels, pedestal noise about 2 ADC channel - If 100 mV signal gives ADC 6 pretty close from noise - will have to optimize gain - ( option to include higher gain in new batch of chip ) 

*SoLID review next week

** need prepare back up slides for DAQ question