May 21st 2020 » History » Version 2
Alexandre Camsonne, 05/21/2020 03:45 PM
| 1 | 1 | Alexandre Camsonne | h1. May 21st 2020 |
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| 2 | |||
| 3 | -updates |
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| 4 | --VMM3 |
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| 5 | 2 | Alexandre Camsonne | ---meeting with USTC, file of board design, Jeff Wilson will help with the board. Ben could |
| 6 | FPGA radiation hard, TMR and SEU triple voting design, Xilinx FPGA space grade around 50 K$, |
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| 7 | ---advised not to use ROC, might try FPGA with redundancy |
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| 8 | ---hardcopy FPGA Altera ? |
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| 9 | --- need table for requirements for experiment |
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| 10 | --- need buffering - for direct readout path - up to 8 us to match FADC |
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| 11 | --- ROC chip ( up to 8 VMM3 ) : VMM3 -> ROC (ASIC) -> GBT |
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| 12 | --- will look into getting ROC chips |
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| 13 | --- FEAST ? replacement DC / DC converter rad hard ( from CERN too ) |
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| 14 | --- still need to compile the analog pulser version |
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| 15 | --FADC : Ed done on FADC side, discussion with Dave on CODA format, working on buffering on FADC and VTP |
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| 16 | --APV25 : tried new firmware with 8 MPDs, 12 connected, issues with some MPDs : MPD omits some channels - update to firmware - need to power cycle crate to reload ( Jack helped ) - seems issue was fixed - more testing - software work around ? |
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| 17 | --ASOC : got pulser and scope for testing |