May 28th 2020 » History » Version 1
Alexandre Camsonne, 05/29/2020 09:44 AM
| 1 | 1 | Alexandre Camsonne | h1. May 28th 2020 |
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| 3 | Agenda : |
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| 4 | -updates |
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| 5 | --prototype board for VMM : computed achievable trigger assumming single rates, assuming 400 ns windows, gives above 100 KHz of trigger rate |
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| 6 | ( 130 KHz if 15 MHz , about 180 KHz if 10 MHz ) could go higher if single rates lower or window smaller. |
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| 7 | Possibility to double e-link for increase bandwidth for the high rate strips. |
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| 8 | Chris : showing FPGA board used for RICH MAROC, could be use as started point |
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| 9 | Time stamp at 160 MHz, gives timestamping at 6 ns resolution |
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| 11 | Need to think about where electronics could be placed, seems VMM better than APV25 because it can handle |
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| 12 | higher capacitance. Will discuss with Kondo and we will do testing. |
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| 14 | Kondo : meeting about VMM production for RD51 SRS, ( 2K$ a wafer ) |
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| 17 | -Compton FADC studies |
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| 19 | -SIDIS trigger requirements - FADC / GEM readout max trigger rate |
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| 20 | Maximum trigger for FADC should be able to reach 200 KHz. |
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| 21 | 2 version of firmware ( triggered for Hall A and B ) , and Hall D firmware - plan for merging two firmware |
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| 23 | -Discussion UMass test stand |