November 12th 2020 » History » Version 2
Alexandre Camsonne, 11/12/2020 03:30 PM
| 1 | 1 | Alexandre Camsonne | h1. November 12th 2020 |
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| 2 | * Updates |
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| 3 | 2 | Alexandre Camsonne | ** VMM3 |
| 4 | *** Ed developing VHDL code to readout the eval board. Expect to be able to read beginning of December |
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| 5 | *** will interface ethernet code |
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| 6 | *** Jeff working on layout |
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| 7 | *** document on Micromegas Card with information for layout and work on noise |
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| 8 | *** Discussion of VMM3 - 16 mV maximum gain - for 100 k electrons and 20 k electrons - 100 K$ to modify the chip - |
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| 9 | *** will scale code from eval board to 128 channels and design triple design TMR for SEU - question from Ben , need to look for a compiler which supports TMR |
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| 10 | ** APV25 |
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| 11 | *** done with APV update, done with simulation for testing with SSP - after will start FADC VXS - can use |
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| 12 | *** estimate delivery mid december |
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| 13 | ** UMass |
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| 14 | *** added missing files - CODA has issues starting VTP ROC - Bryan looking into it |
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| 15 | ** ASOC |
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| 16 | *** spare working - can see |
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| 17 | ** ECAL |
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| 18 | *** need to find 80/20 frame for holding detector and trigger scintillator - need table with 4 layers - Jixie ordering with machine shop - Will check with Jessee |
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| 19 | *** connected Shashlyk to PMT and HV - can see signals |
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| 20 | *** form for Fermilab test beam |
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| 21 | 1 | Alexandre Camsonne | |
| 22 | * preRD quaterly report |