November 5th 2020 » History » Version 2
Alexandre Camsonne, 11/05/2020 03:20 PM
| 1 | 1 | Alexandre Camsonne | h1. November 5th 2020 |
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| 3 | * Updates |
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| 4 | ** VMM |
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| 5 | 2 | Alexandre Camsonne | *** Met with Gianluigi De Geronimo, getting the U Arizona design which is closer to GEM, he was concerned of pick up of DC DC converter by VMM, it seems we expect 100 k to 20 k electrons so we should have |
| 6 | *** discussion of Ed for FPGA to ASIC conversion : SMU people might be able to produce this ASIC. |
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| 7 | *** license Vivado running on Ed computer,can continue development |
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| 8 | *** Jeff still working on layout, will look at AZ design for filtering and shielding of DC supply, connector with low resistance and inductance |
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| 9 | 1 | Alexandre Camsonne | ** APV25 |
| 10 | *** Optical to VXS 32 boards ordered |
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| 11 | *** enable VME320 on SSP readout |
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| 12 | *** show can reach 5 KHz |
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| 13 | 2 | Alexandre Camsonne | **UMass test stand : FADC issue , maximum word loaded is wrong, now decoder works. VTP header files missing which need to be added. |
| 14 | ** ASOC : spare received still need to see signal |
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