October 15th 2020 » History » Version 3
Alexandre Camsonne, 10/15/2020 03:40 PM
| 1 | 1 | Alexandre Camsonne | h1. October 15th 2020 |
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| 2 | * Updates |
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| 3 | ** VMM3 |
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| 4 | 3 | Alexandre Camsonne | *** working with FPGA eval board with VMM3 eval board - can talk the Xilinx Eval board - don't see the direct signal from eval board for now - issue with virtual machine crashing , when plugging things |
| 5 | *** Jeff still working on layout |
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| 6 | *** tried continuous firmware, seems to work, could use the setup to send trigger to channel 63 |
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| 7 | *** L0 max width 8 clock cycles |
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| 8 | 1 | Alexandre Camsonne | ** APV25 |
| 9 | 3 | Alexandre Camsonne | *** testing the rate limit in INFN tomorrow or next week |
| 10 | *** QSFP to VXS out for quoting |
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| 11 | *** multiple 10gigE easier - 10 gigE |
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| 12 | ** UMass : FADC working with CODA, use TI internal trigger and use VTP |
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| 13 | ** MAROC : still noise issue - special windowing to cancel |
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| 14 | |||
| 15 | *Science review talk slides : add plan and status - |
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| 16 | |||
| 17 | *Update SoLID collaboration |