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September 15th 2022 » History » Version 1

Alexandre Camsonne, 09/15/2022 03:36 PM

1 1 Alexandre Camsonne 
h1. September 15th 2022
2 
*Updates VMM
3 
**second QSFP working, second board can be used
4 
**Ben will help debugging second board
5 
**cannot generate pile-up with internal pulser
6 
**could use steps generator
7 
**Xinzhan has readout and decoding programs
8 
**LV rad hard : layout guidelines for bPol
9 





    10
    
    
    
*updates MAROC





    11
    
    
    
**board and LV ready





    12
    
    
    
**SSP board pushed in and fiber connected





    13
    
    
    
**should see 192 signal 





    14
    
    
    
**hardware ready waiting for library to install





    15
    
    
    
** still working on merging libraries





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*ECal





    18
    
    
    
**Getting CAEN FADC