September 17th 2020 » History » Version 4
Alexandre Camsonne, 09/17/2020 04:01 PM
| 1 | 1 | Alexandre Camsonne | h1. September 17th 2020 |
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| 3 | * Updates |
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| 4 | ** VMM3 |
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| 5 | 4 | Alexandre Camsonne | *** prototype : going with larger package for FPGA 95 % certain, has extra IO bank, power and ground assignement next big tasks, several voltages to divide, use model from USTC. |
| 6 | *** evaluation : direct readout, cables done for plugging to FPGA eval board, will test first with current firmware |
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| 7 | *** testing procedure VMM3 : test on wafer, from presentation yield was 72 % |
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| 8 | *** GBT chips order : 35 $ (1 per board, mininum 4 board , have 4 on hand) , fiber optic module plug-in |
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| 9 | *** Ethernet can be used but not very rad hard |
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| 10 | *** eval board : could see data from board |
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| 11 | *** RD51 : |
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| 13 | ** APV25 : |
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| 14 | *** INFN clean room: Bryan looking at how many triggers can be received, SSP processing time quite slow right now. Test with different buffer level, need simulation of MPD to test what is happening. |
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| 15 | Common noise code ready to be set. Right now running 200 Hz need to optimize trigger rules expect 5 KHz if VME is not bottle neck. |
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| 17 | *** Optical adapter should be ready in next few week, ask for quotes : 4 MPDs per board |
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| 19 | ** UMass test stand : not use _ in CODA names |
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| 21 | *Write-up : |
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| 22 | ** update VXS |
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| 23 | ** Milestone E : May 2020 - need update |
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| 31 | 3 | Alexandre Camsonne | ** MAROC |