SoLID DAQ » SoLID preRD

h1. July 2nd 2020

*Updates

**VMM3 : Jeff still working - Neigbhoring channel readout : CERN mapping is different with UVA - UVA is mapped one to one so should work and easy to implement - Radiation tolerance of FPGA : rad hardness for SEL (latchup) up to few 100 krads ( space grade 300 krad ) new FPGA, can design for SEU - support chip rad hardness : DC converter / regulator - 300 krad 5 K$ - regular around 100 $ : data for different experiment , might be able to handle radiation needed - avoid FET based regulator and use bipolar - can supply low voltage directly ( but trickier ) - checking parts which could work

Rad hard FPGA have built-in error correction and more immune to cell SEU

Use 4 bit serial ( 1 bit serial at 70 MHz ) to reload faster - If have GBT, reserve some line for JTAG (GBT full duplex - and has SPI and I2C already )

If SEU to high move FPGA away using cables and / split card VMM FPGA 

Cubesat uses standard components.

**SSP/MPD : check the bad event which might be due to jitter of clock - 12 MPDs 1 Millions events - 2.5 GBit /s : 1 bit corrupted from time to time - was not seen on other setup at 5 g bit so might be on MPD side - scope installed on system - 250 Hz right now - SSP can process data as MPD is sending gives 10 kHz trigger rate for 6 samples - 

Received 4 to 1 fibers  will ask to Xin

**MAROC : seven assemblies and got it to run, some noise but small compared to single photon , and operated will Hall B CODA 

          NIM modules for analog output : 9 outputs  for 192 channels 

*Beam July 27th : need evaluate time for installation              

*NALU designing board for ASOC for ALERT - same protocol as RICH

!https://redmine.jlab.org/attachments/download/1016/IMG_20191203_210642.jpg!

!https://redmine.jlab.org/attachments/download/1017/IMG_20191203_210632.jpg!

!https://redmine.jlab.org/attachments/download/1018/IMG_20191203_210711.jpg!

!https://redmine.jlab.org/attachments/download/1019/IMG_20191203_210726.jpg!