July 30th 2020 » History » Version 3
Alexandre Camsonne, 07/30/2020 03:41 PM
| 1 | 1 | Alexandre Camsonne | h1. July 30th 2020 |
|---|---|---|---|
| 2 | |||
| 3 | *Updates |
||
| 4 | 2 | Alexandre Camsonne | **VMM3 : Jeff continuing on routing, tricky for inner pins - differential data line not super high speed but need to be well designed for 320 Mbit - |
| 5 | Discussed with Hai - Ultrascale Eval board will be used to use with VMM eval board |
||
| 6 | Going back to evaluation board next week, will try latest software Bryan compiled |
||
| 7 | 1 | Alexandre Camsonne | |
| 8 | 2 | Alexandre Camsonne | https://redmine.jlab.org/attachments/download/1010/vmm_readout_software-analog_generator-COMPILED.tgz |
| 9 | 1 | Alexandre Camsonne | |
| 10 | 2 | Alexandre Camsonne | Waiting for BNL order |
| 11 | ROC chip : trying to contact to evaluate cost of making an ASIC - still need special design for ASIC to get them radiation hard in addition to TMR |
||
| 12 | |||
| 13 | 3 | Alexandre Camsonne | **APV25 : Ben still investigating - tried adding new oscillator - did not help - still jitter - most likely because of noisy power line |
| 14 | data line gets corrupted when data is sent |
||
| 15 | analog pll from general power rail ( not good because noise ) - voltage shift |
||
| 16 | 2 | Alexandre Camsonne | - will try to add more capacitance to reduce the shift , if does not work, go to half speed 1.25 Gbps |
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | |||
| 21 | 1 | Alexandre Camsonne | *SoLID review talks |
| 22 | 2 | Alexandre Camsonne | ** GEM readout talk |