March 21 2024 » History » Version 3
Alexandre Camsonne, 03/21/2024 02:02 PM
1 | 1 | Alexandre Camsonne | h1. March 21 2024 |
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3 | 2 | Alexandre Camsonne | * Updates VMM |
4 | 3 | Alexandre Camsonne | ** Working on L0 mode - Hall B planning to use |
5 | ** Purchase for rad hard component for LHC : lpGBT and VTR+ and bPol 2.5 - for TDIS and SoLID - in queue for 14 months - letter of increase added because cost went up - increase quantity to have the SoLID ones - might be coming soon : lpGBT and bPol (2.5 -> 2.5 to 1.2) and bPol12 might come in a week - could make the radhard mezzanine - could use bPol for PRAD and SBS - can test and measure noise - |
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6 | ** VTR+ later |
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7 | ** interface from benchtop supply: design complete - still not ordered - need to be careful of spike at start - could ramp the supply |
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8 | ** Hall B has untested VMM - wants to make a 4 chips prototype - one engineer will test the VMM - will use one eval board with socket to test chips |
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9 | ** need to replace the desiccant for VMM |
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10 | ** SALSA : 50 MHz FADC - |
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11 | ** MPD - new version - |
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12 | ** Pixel chamber GEM - different pixel size - ~ 100 k channels |
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13 | ** check with Paolo, new MPD |
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14 | ** APV25 220nm process - SAMPA 120 ns - SALSA 65 nm - check if line still exist |
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15 | 1 | Alexandre Camsonne | * Status orders |
16 | 3 | Alexandre Camsonne | ** FADC ordered |
17 | ** VTP ordered |
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18 | ** TI |
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19 | 1 | Alexandre Camsonne | ** SD |
20 | 3 | Alexandre Camsonne | ** VXS - 24 ordered need 8 more |
21 | 1 | Alexandre Camsonne | ** VETROC |
22 | * MRPC electronics |
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23 | 2 | Alexandre Camsonne | ** NALU ASOC and AARDVARC |
24 | ** picoTDC |
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25 | 3 | Alexandre Camsonne | ** SAMPIC |
26 | *TDIS |
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27 | **wirechamber - 1 ns |
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28 | **SAMPA close to 2 ns with fitting of pulse at 20 MHz |