May 6th 2021 » History » Version 3
Alexandre Camsonne, 05/06/2021 03:54 PM
| 1 | 1 | Alexandre Camsonne | h1. May 6th 2021 |
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| 2 | 2 | Alexandre Camsonne | * Updates |
| 3 | ** VMM |
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| 4 | 3 | Alexandre Camsonne | *** VHDL code at 1 gbit speed, going through GBT with 10 serial lines |
| 5 | *** PCB : working on power distribution, added signal lines with mezzanine to save space on board, move flash memory to mezzanine and JTAG |
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| 6 | *** can make progress on VMM design rapidly |
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| 7 | *** do not need to have both ethernet or GBT at same time so can save |
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| 8 | *** 1 FPGA received from NewArk |
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| 9 | *** some FPGA ordered from unauthorized source : cancelled - only 30 days warranty |
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| 10 | *** new order should arrive before 30 weeks lead time |
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| 11 | *** can use 040 or 035 : development board using 040 abour 3K$, could order a few (AVNET has 12 ) |
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| 12 | *** 4 chips : new order with AVNET through for regular FPGA, might get those in time (30 to 35 weeks ) |
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| 13 | *** could check for other board with this chip |
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| 14 | *** need to follow up on special parts with Nilanga ( might be able to use some spare parts from SAMPA but needs to replenish stock ) |
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| 15 | *** VMM in customs |
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| 16 | *** Need to follow up with George |
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| 17 | ** APV |
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| 18 | *** VTP readout completed |
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| 19 | *** MPD APV readout still need to fix issues |
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| 20 | ** FADC |
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| 21 | *** 2 FADC readout - need add CODA GUI for controls |
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| 22 | *** no performance test yet |
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| 23 | **UMass |
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| 24 | *** took asymmetry test data, writing software |
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| 25 | **VMM |
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| 26 | *** test with chamber in UVA in EEL clean room |
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| 27 | *** getting starting with UVA setup for X-ray |
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| 28 | *** adapter for the VMM eval board for direct |
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| 29 | ** |
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| 30 | *start to think about CD1 needs |
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| 31 | *streaming workshop : quickly put number together SIDIS seems doable - need to do some studies |